The present invention concerns a semiconductor integrated circuit device and a manufacturing technique thereof and, more particularly, it relates to a technique which is effective when applied to a device using BPSG (Boron-Doped Phospho Silicate Glass) film for a portion of an interlayer insulation film.
Along with reduction of the size and increase in the integration degree of LSI devices, an undesirable side-effect has been an increase in the size of wiring steps of such semiconductor devices. For instance, large capacity DRAMs (Dynamic Random Access Memory) in recent years have used a stack capacitor structure for compensating the reduction of a storage charge amount (Cs) of an information storage capacitance device which typically takes place with size reduction of a memory cell. In such a stack capacitor structure, the information storage capacitance device is disposed above a memory cell selecting MISFET. As a result, a step corresponding substantially to the height of the information storage capacitance device is formed between a memory array and a peripheral circuit. Further, such a step is formed also in a region of the memory array and the region of the peripheral circuit.
If wirings are formed on such a step, defocusing of exposure light is caused upon photolithography or an etching residue is formed at the step, so that wirings cannot be formed with high accuracy. This can cause failures such as short-circuiting or disconnection.
For overcoming the foregoing problems, it is essential to provide a technique capable of flattening an interlayer insulation film that insulates wirings in a lower layer and wirings in an upper layer. For the flattening of the interlayer insulation film, various methods have been developed. Examples of such techniques include a method of using a BPSG film or a spin on glass film having high reflowing property, a bias ECR plasma CVD method of simultaneously conducting film formation and sputter etching, or a chemical mechanical polishing method.
For instance, Japanese Patent Laid-Open No. Hei 7-122654 provides a DRAM designed for reduction of steps by the combination of flattening by a BPSG film by reflowing and flattening using a spin-on-glass film. The BPSG film comprises boron (B) containing silicon oxide and phosphorus (P) each by several mol %. The surface the film after formation by a CVD method is flattened by annealing reflow. In a case of using the spin-on-glass film, a silicon oxide film is at first deposited by a plasma CVD method, then a spin-on-glass film is deposited thereon by a rotary coating method. Subsequently, the spin-on-glass film is baked to densify the film, then the surface of the film is flattened by etching back and, further, a silicon oxide film is deposited on the surface by a plasma CVD method to form a flat interlayer insulation film.
In a production process for such an LSI, a semiconductor wafer having LSI formed thereon is subjected to dicing, and is divided into semiconductor chips. These chips are attached one by one to a lead frame (pellet attaching), subjected to wire bonding and then encapsulated with a molding resin.
Since the dicing for the semiconductor wafer is mechanically applied by using, for example, a diamond blade, fine cracks are formed at side walls of the semiconductor chip along which moisture or obstacles may intrude to the inside of the chip to bring about corrosion of the wirings. In order to prevent this, a guard ring is usually provided around the periphery of the semiconductor chip. The guard ring is formed by burying a wiring material for the circuit (aluminum alloy or tungsten) along the inside of a groove formed along the periphery of the semiconductor chip, whereby moisture or obstacles intruding from the side wall of the chip are interrupted from further invasion into the chip by the wiring material.
In a case of using a BPSG film for a portion of the interlayer insulation film, it has been found by the study of the present inventors that if the concentration of boron (B) in the film is higher than a certain level, cracks generated at the end of the chip reach the inside of the chip penetrating the guard ring and, as a result, moisture or the like intrudes through the cracks into the chip to bring about corrosion of wirings. As the result of these studies, it has been found that the relationship between the boron concentration in the BPSG film and the cracks formed at the end of the chip is substantially as discussed below.
FIG. 12(a) is a graph showing the result of the study for a relationship between the boron concentration in the BPSG film (unit: mol %) and reflow angle (.theta.) on the side wall of the wiring in a case such as shown in FIG. 12(b) of depositing a BPSG film by a CVD method on a substrate having wirings formed thereon and applying reflow. The thickness of the wiring is 0.6 .mu.m and reflow conditions are 850.degree. C. for a period of 20 minutes. Further, since the concentration of phosphorus in the BPSG film has less effect on the reflow angle as compared with the boron concentration, it is set to 6 mol %. As shown in the graph, the reflow angle (.theta.) is increased and the film flatness is improved as the boron concentration in the BPSG film becomes higher.
It can be seen from the result described above that, since the wiring step undesirably is increased with reduction of the size and increase of the integration degree of an LSI device, the boron concentration in the film has to be made higher for ensuring the flatness of the BPSG film. Further, for reducing the size and increasing the integration degree of such an LSI device, the depth of the pn junction such as in source and drain regions of MISFETs of the device has to be decreased, and annealing for the BPSG film has to be conducted at a lower temperature for attaining a shallow junction. However, the film reflowing property is deteriorated as the annealing temperature is lowered. Accordingly, the concentration of boron in the film has to be increased for ensuring satisfactory reflowing properties at the lower temperature.
For instance, in a 4 Mbit DRAM manufactured using a 0.8 .mu.m design rule, a BPSG film of 7 to 8 mol % of boron concentration is annealed at a temperature of about 950.degree. C. In a case of a 16 Mbit DRAM manufactured using about a 0.5 .mu.m design rule, since an equivalent or higher reflowing property has to be ensured, it is required to apply annealing at a temperature of about 850.degree. C. in view of the improvement for the performance of transistors. For this purpose, it is necessary to use a BPSG film having a boron concentration higher than 10 mol %, and it is preferable to use a BPSG film containing boron at about 13 mol % taking into account variations of the boron concentration.
Unfortunately, notwithstanding the above-discussed advantages, it has been found that the following problems are brought about as the boron concentration in the BPSG film is made higher. FIG. 13 is a graph showing the result of a relationship between the boron concentration (unit: mol %) in a BPSG film and wiring failure rate caused by occurrence of cracks at the end of the chip. As shown in the graph, if the boron concentration in the BPSG film exceeds about 15 mol %, the failure rate increases abruptly.
As a reason for this drawback, it may be considered that when the boron concentration in the BPSG film is higher, the hygroscopic property of the film is increased. Therefore, if an insulation film (for example, a silicon oxide film deposited by a plasma CVD method) is deposited on the moisture absorbing film, since adhesion with the insulation film is lowered, minute cracks generated at the chip end during dicing grow along the boundary of the film to the inside of the chip. This can occur, for example, during high temperature high humidity testing of packages (a standing test under a circumstance, for example, at a temperature of 85.degree. C. and humidity of 85%).
It may be also considered that a dense and hard insulation film such as a silicon nitride film deposited by a plasma CVD method is used as the material of a passivation film covering the surface of a semiconductor chip in order to protect the inside of the chip. However, the passivation film constituted with such a material has a high film rigidity which creates a large stress on the underlying interlayer integration film. This accelerates the growth of any cracks that may have been created.
Namely, it is assumed that if the boron concentration in the BPSG film is increased to about 15 mol %, the film absorbs moisture when connection holes are formed in a state where the surface of the film is exposed or when wirings are formed by patterning a metal film deposited on the film. If the insulation film is deposited on the moisture absorbing BPSG film, the adhesion at the boundary of the film is lowered, and minute cracks generated at the end of the chip grow along the boundary. Then, growth of the cracks is further accelerated by stresses from the highly rigid passivation film. These cracks cut the guard ring and can reach as far as the inside of the chip, so that the water proofing function of the guard ring is lost, resulting in corrosion of wirings.
This problem is shown in FIG. 16, for example, which also shows the phenomenon of peeling.
Specifically, FIG. 16 shows an arrangement wherein a BPSG silicon oxide film 20 having a high boron concentration is formed on a semiconductor substrate 1. An additional insulating film (not containing boron), such as a TEOS film 23, is formed on the BPSG film 20, and a hard passivation film, such as P-SiN film 26 is formed over the insulating film 23. As discussed above, the high concentration of boron in the BPSG film 20 causes poor adhesion between the film 20 and the overlaying insulator 23. This leads to separation cracks between the two layers in the area between the guard ring and the edge of the chip. Due to the extreme hardness of the overlying P-SiN layer 26, the separation cracks between the layers 20 and 23 tend to extend inside the area of the guard ring, thereby permitting moisture to undesirably reach inside of the device.
As described above, in a case of the 16 Mbit DRAM manufactured using about a 0.5 .mu.m design rule, it is required to use a BPSG film containing about 13 mol % of boron. Therefore, the boron concentration in the film is increased to a concentration which can bring about deterioration of the film adhesion (about 15 mol %) depending on the condition of forming the BPSG film. Accordingly, there is a possibility of causing wiring corrosion due to cracks.
From the foregoing discussion, in a case of using a BPSG film containing boron at high concentration for a portion of the interlayer insulation film material in a device manufactured using a 0.5 .mu.m or finer design rule, a countermeasure is indispensable for preventing wiring corrosion caused by cracks along the boundary of the film described above.